1. Field of the Invention
The present invention generally relates to electrical rectifying circuits and, in particular, to rectifying circuit that uses a transistor as a rectifier.
2. Description of the Prior Art
In power converters, synchronous rectifier MOS (SRMOS) transistors are used and operated in such a manner to perform like a diode, allowing conduction in one direction and preventing conduction in the opposite direction. The advantage with using an SRMOS transistor in the place of a diode is the higher efficiency obtainable with an SRMOS--namely the avoidance of the voltage drop across a conventional diode. This advantage becomes increasing important as greater demand and operation time is demanded from a limited power source such as batteries. In the case of a converter circuit, it becomes even more crucial that there is minimal voltage drop in converting one voltage level to another voltage level. Otherwise, a great deal of power would be lost in the conversion process itself.
Traditionally, SRMOS are controlled by several methods. Referring to FIG. 1a, a prior art converter circuit with a SRMOS is illustrated. This circuit is comprised of a first transistor 10 having gate, drain and source terminals, and the transistor is connected at one terminal to a voltage source having a particular voltage level and is connected at another terminal in series to a coil 12, and to a capacitor 16. A second transistor 18, being operated as a synchronous rectifier (SRMOS), is connected at one terminal to a node between the first transistor 10 and the coil 12 and is connected at another terminal to the common ground terminal. A pulse width modulation (PWM) control circuit 20, having a probe at the output terminal 22, detects the output voltage level. The PWM control circuit operates transistors 10 and 18 in response to the detected voltage level and causes the generation of the desired voltage level at the output terminal. Transistors 10 and 18 are controlled by a common signal and transistor 18 is connected via an inverter 14. When transistor 10 is turned on, transistor 18 is turned off. In some cases, an optional external diode is placed across transistor 10.
In this type of circuit, referring to FIG. 1b illustrating the gate voltage for transistor 10 (which is being operated as the main switch for generating the desired output voltage level) and FIG. 1c illustrating the gate voltage in operating the SRMOS (transistor 18) and FIG. 1d illustrating the current in the inductor 12, the SRMOS (transistor 18) is turned on whenever the main converter switch (transistor 10) is turned off (as indicated at 24), and the SRMOS (transistor 18) is turned off whenever the main converter switch (transistor 10) is turned on. While this is a simple arrangement, when the SRMOS is turned on, there is a large amount of reverse conduction (current flow indicated at 28) that reduces overall converter efficiency.
In yet another prior art circuit, referring to FIG. 2a, a SRMOS converter circuit using the current sense control method is illustrated. This circuit is comprised of a first transistor 30 having gate, drain and source terminals, where the transistor is connected at one terminal to a voltage source having a particular voltage level and is connected at another terminal in series to a coil 32, a shunt 34 (for current sensing), and a capacitor 36. A second transistor 38, being operated like a synchronous rectifier, is connected at one terminal to a node between the first transistor 30 and the coil 32 and is connected at the other terminal to the common ground terminal. A pulse width modulation (PWM) control circuit 40, having two probes for current sensing across the shunt 34 and a probe at the output terminal 42, detects the current level and the output voltage level. The PWM control circuit operates transistors 30 and 38 in response to the detected voltage and current levels and causes the generation of the desired voltage level at the output terminal 42.
In this type of circuit, referring to FIG. 2b illustrating the timing of the gate voltage for transistor 30 and FIG. 2c illustrating timing of the gate voltage in operating the SRMOS (transistor 38) and FIG. 2d illustrating current flow of the inductor, in the discontinuous mode when there is reverse conduction and the inductor current starts to flow in the negative direction through the SRMOS (transistor 38), current flow is sensed through the use of the shunt 34. The control circuit 40 sensing reverse conduction turns off the SRMOS (transistor 38) to prevent further reverse conduction. However, since the shunt resistance is typically very small, it is difficult to precisely detect the timing of the zero crossing of the current. Thus, the SRMOS is turned off either before the zero crossing or after the zero crossing, rendering this an imprecise method. Because this is an imprecise method, there still may be a large amount of negative current flow (as indicated in FIG. 3d, 48). Additionally, the shunt is a resistor which consumes power as well (lossy). While the typical shunt resistor is 33 m.OMEGA. and the power consumption can be reduced by using a shunt with even smaller resistance, with a smaller shunt, there will be more reverse conduction before the negative current can be detected. Overall, this circuit is not a reliable nor efficient converter circuit.
In still yet another prior art circuit, referring to FIG. 3a, a SRMOS converter circuit using Vds sensing control method is illustrated. This circuit is comprised of a first transistor 50 having gate, drain and source terminals, where the transistor is connected at one terminal to a voltage source having a particular voltage level and is connected at another terminal in series to a coil 52, and the coil is connected to a capacitor 56. A second transistor 58, being operated like a synchronous rectifier, is connected at one terminal to a node between the first transistor 50 and the coil 52 and is connected at the other terminal to the common ground terminal. A pulse width modulation (PWM) control circuit 60, having a probe 54 for voltage sensing at a node between transistor 50 and coil 52 and a probe at the output terminal 62, detects the Vds level and the output voltage level. The PWM control circuit operates transistors 50 and 58 in response to the detected voltage levels and causes the generation of the desired voltage level at the output terminal 62.
FIG. 3b illustrates the timing of the gate voltage for transistor 50 of FIG. 3a, FIG. 3c illustrates timing of the gate voltage in operating the SRMOS (transistor 58) in view of the FIG. 3b, and FIG. 3d illustrates current flow of this circuit. In this type of circuit, in the discontinuous mode when there is reverse conduction and the inductor current starts to flow in the negative direction through the SRMOS (transistor 58), the SRMOS drain voltage (Vds) becomes positive which is sense by the control circuit 60 and the control circuit turns the SRMOS off. However, in practice, precise Vds sensing is difficult and reverse conduction occurs (as shown in FIG. 3d, 64), rendering this type of circuit unreliable and inefficient.
Given the state of the art and the demand for a more efficient converter circuit, it would be desirable to have a method and circuit that can perform rectifying function and prevent the occurrence of reverse conduction through the use of a transistor.